How Are High-Speed Cables Routed Inside AI Servers? GPU, NIC, Switch, and Cable Architecture Explained｜Technology Year：2022

Inside an AI server, not all high-speed data travels through the same cable or interconnect path.

A multi-GPU AI server typically contains several different high-speed data paths, including:

GPU ↔ GPU
CPU ↔ GPU
GPU ↔ NIC / DPU
NIC / DPU ↔ External Network
Storage ↔ CPU / GPU

The real design question is therefore not:

“Which high-speed cable should an AI server use?”

It is:

Which signals should remain on the PCB, which should use NVLink or PCIe, and which should transition to board-to-board connectors or internal high-speed cables to balance bandwidth, reach, Signal Integrity, mechanical space, and cooling?

Modern AI servers combine multiple interconnect technologies because different data paths have different performance and physical requirements.

What Are the Main High-Speed Data Paths Inside an AI Server?

The first key distinction is:

Internal chip-to-chip interconnects and cables that route signals from a NIC or other device to a chassis I/O port are not the same thing.

In some AI server architectures, the GPU-to-GPU path remains tightly integrated on a GPU baseboard, while network signals are routed through internal cables from networking cards to front or rear I/O connectors.

How Does Data Move Between GPUs, NVSwitches, and NICs?

A simplified Scale-Up path may look like:

GPU
↓
NVLink / NVSwitch
↓
Other GPUs

At the same time, a Scale-Out path may look like:

GPU
↓
PCIe
↓
NIC / DPU
↓
Internal High-Speed Cable
↓
OSFP / QSFP Port
↓
DAC / AEC / Optical
↓
Data Center Switch

These two paths solve very different problems.

GPU ↔ GPU: Scale-Up Communication

GPU-to-GPU communication requires extremely high bandwidth and very low latency.

Technologies such as NVLink and NVSwitch are designed to connect multiple GPUs into a tightly coupled compute domain.

This does not mean that each GPU is necessarily connected to an NVSwitch through a conventional visible cable.

In many systems, Scale-Up links are integrated into:

GPU Baseboards
PCB Routing
High-Density Board Connectors
Dedicated Interconnect Structures

depending on the platform architecture.

GPU ↔ NIC / DPU: Scale-Out Exit

When GPU data needs to travel to another server, it typically enters the networking subsystem.

A simplified path is:

GPU Memory
→ PCIe
→ NIC / DPU
→ Network

Technologies such as GPUDirect RDMA can reduce unnecessary CPU and host-memory involvement by allowing compatible network devices to communicate more directly with GPU memory.

This makes the:

GPU ↔ PCIe ↔ NIC

path one of the most important high-speed paths inside an AI server.

Why Not Route Every High-Speed Signal Through the PCB?

As SerDes data rates increase, long PCB traces consume more of the available channel-loss budget.

Key challenges include:

This is why high-speed server platforms increasingly use:

Flyover Cable Architecture

The idea is not to replace every PCB trace with cable.

Instead:

A high-speed signal can leave the PCB earlier, travel through a lower-loss cable across a longer physical distance, and re-enter the PCB closer to the destination connector, switch, or I/O device.

This can reduce the amount of lossy PCB routing required for high-speed lanes.

What Types of Internal High-Speed Interconnects Are Used?

AI server designs may combine several different physical interconnect architectures.

Therefore, AI server interconnect architecture is better understood as:

PCB + Connector + Cable

working together, rather than:

Cable replacing PCB.

Why Is NIC-to-OSFP / QSFP Routing Well Suited to Internal Cables?

A NIC or DPU is not always physically located directly behind the server's external I/O port.

If the networking device is positioned deeper inside the chassis, routing the signal entirely through the motherboard may require:

**Longer PCB Traces

• More Vias
• More Layer Transitions
• Greater Channel Loss
• More Routing Complexity**

An internal high-speed cable can instead create a more direct path:

NIC / DPU
→ Internal Cable
→ OSFP / QSFP Connector

The external port can then connect to the data center network using:

DAC
AEC
AOC
Optical Transceiver

A complete Scale-Out physical path may therefore look like:

GPU → PCIe → NIC → Internal Cable → OSFP / QSFP → External Cable or Optics → Network Switch

This is an important reason internal cable assemblies have become increasingly relevant in high-density AI servers.

Where Do PCIe Switches and Retimers Fit?

Modern AI servers often contain many PCIe devices, including:

• GPUs
• NICs
• DPUs
• NVMe SSDs
• Accelerators

A:

PCIe Switch

may be used to manage lane topology and connectivity between these devices.

If a high-speed PCIe channel becomes too long or electrically difficult, a:

PCIe Retimer

can recover clock and data and divide one difficult channel into multiple manageable electrical segments.

A simplified topology may look like:

CPU
→ PCIe Switch / Retimer
→ GPU / NIC / Storage

Some physical segments may use PCB traces, while others may use connectors and cable assemblies.

This means an AI server should not be viewed as a simple:

CPU → GPU

connection.

It is a multi-layer high-speed interconnect system.

Which Signal Integrity Parameters Matter Most for Internal AI Server Cables?

A cable fitting mechanically is only the first requirement.

The high-speed channel must also maintain electrical performance.

Therefore, simply specifying:

“PCIe Gen5 Cable”

or:

“400G Cable”

is not enough.

The complete design must also consider:

**Data Rate per Lane

• Lane Count
• Channel Budget
• Connector
• Cable Length
• Retimer
• Host Compatibility**

Why Are Cable-Based Architectures Becoming More Important in AI Servers?

AI servers continue increasing:

**GPU Count

• NIC Bandwidth
• PCIe Speed
• Network Port Speed**

At the same time, system designers must manage:

**More High-Speed Lanes

• Higher Signal Frequencies
• Limited PCB Space
• Higher Power Density
• More Difficult Cooling**

As a result, routing every high-speed signal across the full motherboard is not always the most efficient solution.

Modern AI hardware increasingly combines:

**GPU Baseboards

• PCIe Switches
• Retimers
• Board-to-Board Connectors
• Flyover / Internal Cables
• High-Speed I/O**

to create modular and manageable high-speed architectures.

However, there is no universal cable layout for every AI server.

Different GPU platforms, CPUs, accelerators, OEM designs, and ODM systems may use different:

• PCIe topologies
• GPU baseboards
• NIC locations
• Rear or front I/O layouts
• Cable routing strategies

The most important engineering principle is:

There is no single fixed rule for where an internal high-speed cable must run. The physical route must follow the complete system topology and channel requirements.

AI Server Internal High-Speed Cabling: Key Takeaways

The four most important points are:

First, AI servers contain multiple high-speed paths, including GPU-to-GPU, CPU-to-GPU, GPU-to-NIC, and NIC-to-I/O connections.

Second, GPU-to-NVSwitch links do not necessarily use conventional cables; many Scale-Up interconnects are integrated into GPU baseboards and board-level structures.

Third, internal high-speed cables are especially useful for routing signals from NICs, switches, retimers, or other high-speed devices across longer physical distances to I/O connectors while avoiding excessive PCB loss.

Fourth, the purpose of cable-based architecture is to balance PCB loss, Signal Integrity, mechanical space, cooling, serviceability, and cost.

A complete AI server high-speed data path should therefore be understood as:

**GPU

• NVLink / NVSwitch
• PCIe
• NIC / DPU
• Retimer / PCIe Switch
• Internal Cable
• OSFP / QSFP
• External Network**

High-speed cables are not isolated components.

They are part of the AI server's:

System-Level Interconnect Architecture

and must be designed together with the PCB, connectors, SerDes, switches, and equipment topology.

SyncTronics Solutions

Internal high-speed interconnects for AI servers should be evaluated according to GPU, NIC / DPU, PCIe switch, retimer, I/O port, lane rate, cable length, and complete Signal Integrity requirements. SyncTronics can support specification verification and NPI evaluation for high-speed Cable Assemblies, connectors, Twinax, PCIe, and customized electronic interconnect solutions for AI servers, networking equipment, data centers, and high-performance computing platforms.

Related Articles

• What Are Scale-Up and Scale-Out in AI Data Centers? A Complete Guide to GPU High-Speed Network Architecture
• Ethernet vs InfiniBand: How Should AI GPU Clusters Choose a High-Speed Network?
• Retimer vs Redriver vs AEC: A Complete Guide to High-Speed Signal Extension Technologies
• High-Speed DAC Cable Structure Explained: Twinax, AWG, Shielding, and Signal Integrity

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